DS1033 3in1 low voltage silicon delay line DS1033 021798 1/6 features ? allsilicon timing circuit ? three independent buffered delays ? initial delay tolerance 1.5 ns ? stable and precise over temperature and voltage ? leading and trailing edge precision preserves the input symmetry ? standard 8pin dip, 8pin soic ? vapor phasing, ir and wave solderable ? available in tape and reel pin assignment v cc 1 2 3 4 8 7 6 5 out1 out2 out3 in1 in2 in3 gnd 1 2 3 4 8 7 6 5 gnd in3 in2 in1 out1 out2 out3 v cc DS1033z 8pin soic (150 mil) DS1033m 8pin dip see mech. drawings section see mech. drawings section pin description in1in3 input signals out1out3 output signals nc no connection v cc supply voltage gnd ground (sub) internal substrate connection, do not make any external connec- tions to these pins description the DS1033 series is a lowpower +3.3 volt version of the ds1035. it is characterized for operation over the range of 2.7v to 3.6v. the DS1033 series of delay lines have three indepen- dent logic buffered delays in a single package. it is avail- able in a standard 8pin dip, 150 mil 8pin minisoic. the device features precise leading and trailing edge accuracies. it has the inherent reliability of an allsilicon delay line solution. the DS1033's nominal tolerance is 1.5 ns and an additional tolerance over temperature and voltage of 1.0 ns for the faster delays. detailed specifications are shown in table 1. standard delay values are indicated in table 1. cus- tomers may contact dallas semiconductor at (972) 3714348 for further information.
DS1033 021798 2/6 logic diagram figure 1 time delay in out one of three part number delay table (t plh , t phl ) table 1 part number delay per output (ns) initial tolerance tolerance over temperature and voltage (note 2) part number output (ns) (note 1) tolerance (note 1) v cc =3.3v 0.3v v cc =2.7v DS10338 8/8/8 1.5 ns 1.0 ns 1.5 ns DS103310 10/10/10 1.5 ns 1.0 ns 1.5 ns DS103312 12/12/12 1.5 ns 1.0 ns 1.5 ns DS103315 15/15/15 1.5 ns 1.5 ns 2.0 ns DS103320 20/20/20 1.5 ns 1.5 ns 2.5 ns DS103325 25/25/25 2.0 ns 2.0 ns 3.5 ns DS103330 30/30/30 2.0 ns 2.0 ns 5.0 ns notes: 1. nominal conditions are +25 c and v cc =+3.3 volts. 2. temperature range of 0 c to 70 c. 3. delay accuracy is for both leading and trailing edges.
DS1033 021798 3/6 test setup description figure 2 illustrates the hardware configuration used for measuring the timing parameters of the DS1033. the input waveform is produced by a precision pulse gener- ator under software control. time delays are measured by a time interval counter (20 ps resolution ) connected to the output. the DS1033 output taps are selected and connected to the interval counter by a vhf switch con- trol unit. all measurements are fully automated with each instrument controlled by the computer over an ieee 488 bus. DS1033 test circuit figure 2 pulse generator time interval counter start 50 w 50 w stop out outputs 13 unit under test vhf switch control unit 3in
DS1033 021798 4/6 absolute maximum ratings* voltage on any pin relative to ground 1.0v to +6.0v operating temperature 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds short circuit output current 50 ma for 1 second * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (t a =0 c to 70 c) parameter symbol test condition min typ max units supply voltage v cc 2.7 3.3 3.6 v active current i cc v cc =3.6v period=1 m s 25 ma high level input voltage v ih 2.0 v cc +0.5 v low level input voltage v il 0.5 0.8 v input leakage i l 0v< v i < v cc 1.0 1.0 m a high level output current i oh v cc =2.7v v oh =2v 1.0 ma low level output current i ol v cc =2.7v v ol =0.4v 8 ma ac electrical characteristics (t a =+25 c) parameter symbol min typ max units notes period t period 2 (t wi ) ns 2 input pulse width t wi 100% of tap delay ns 2 inputtotap output delay t plh, t phl table 1 ns output rise or fall time t or , t of 2.0 3.0 2.5 3.5 ns ns 3 4 powerup time t pu 100 ms capacitance (t a =25 c) parameter symbol min typ max units notes input capacitance c in 10 pf
DS1033 021798 5/6 test conditions ambient temperature: 25 c 3 c supply voltage (v cc ): 3.3v 0.1v input pulse: high: 3.0v 0.1v low: 0.0v 0.1v source impedance: 50 w max. rise and fall time: 3.0 ns max. measured between 0.6v and 2.4v. pulse width: 500 ns pulse period: 1 m s output load capacitance: 15 pf output: each output is loaded with the equivalent of one 74f04 input gate. data is measured at the 1.5v level on the rising and falling edges. note: the above conditions are for test only and do not restrict the devices under other data sheet conditions. timing diagram 1.5v 1.5v 1.5v 1.5v 1.5v in t fall t rise 80% 20% t plh t phl out t wi t wi period notes: 1. all voltages are referenced to ground. 2. pulse width and duty cycle specifications may be exceeded, however, accuracy will be application sensitive with respect to decoupling, layout, etc. 3. v cc =3.3v 10%. 4. v cc =2.7v.
DS1033 021798 6/6 terminology period : the time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t wi (pulse width): the elapsed time on the pulse between the 1.5 volt point on the leading edge and the 1.5 volt point on the trailing edge or the 1.5 volt point on the trailing edge and the 1.5 volt point on the leading edge. t rise (input rise time): the elapsed time between the 20% and the 80% point on the leading edge of the input pulse. t fall ( input fall time): the elapsed time between the 80% and the 20% point on the trailing edge on the input pulse. t plh (time delay, rising): the elapsed time between the 1.5 volt point on the leading edge of the input pulse and the 1.5 volt point on the leading edge of the output pulse. t phl (time delay, falling): the elapsed time between the 1.5 volt point on the falling edge of the input pulse and the 1.5 volt point on the falling edge of the output pulse.
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